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Ballistic Deflection Devices

This research project involves the investigation of ballistic electron transport properties in high ¨C mobility III-V semiconductors and further looks at how to exploit these effects to realize ultra ¨C low power logic devices. Emerging nanoscale devices, charge or alternate state variable based, exhibit very low intrinsic gain at reduced operating voltage conditions, making it essential to reconsider device design in conjunction with new logic representation. In this project we are exploring a novel interconnect-less binary decision diagram (BDD) logic architecture based on ballistic propagation of electrons in the so called Y-junction switch. The proposed architecture a) circumvents the need to charge and discharge load capacitances at each node in the logic tree thus dramatically reducing propagation delay, b)reduces wiring related energy loss while maintaining logic functionality under tens of millivolts of supply voltage, and c) operates with ultra-low energy-delay product. BDD architecture lends itself well towards design with ballistic Y-junction and nanowire devices. Our ongoing theoretical and experimental research is investigating whether this approach is indeed suitable for augmenting/replacing CMOS logic at ultra ¨C low supply voltages. This program is supported by a federal government agency.