Home > Research > Inter-band Tunnel Transistors and Related Circuits

Inter-band Tunnel Transistors and Related Circuits

This research is directed at demonstrating the minimum energy-delay product performance of inter-band tunneling transistors that can be realized by using narrow and direct gap high mobility heterostructure materials, such as InxGa1-xAs (0.53 < x < 1) . The goal of this research is to create a non-equilibrium distribution of carriers via inter-band tunneling process from degenerately doped source region into the channel with the high/low energy portions of the Fermi-Dirac distribution filtered by the valence/conduction band edges of the source and channel semiconductor, respectively. This can result in sub kT/q steep sub-threshold slope transistors with high Ion-Ioff over a limited gate voltage swing (<0.35V). The key research challenge is to experimentally demonstrate a tunnel transistor with acceptable on-current by enhancing the source-side tunnel injection coefficient. This can be achieved by an optimal combination of narrow/direct gap, low effective mass material system, band-gap engineering using heterostructure, sharp doping profile in conjunction with low temperature processing, phonon engineering, low EOT dielectric integration and finally, multiple gate architecture with efficient gate-to-channel coupling. Our ongoing research addresses several open questions through a combination of theory and experiments: Can abrupt doping profile be maintained throughout fabrication process? Can a high quality ultra-thin high-k dielectric be integrated in a vertical transistor configuration? What is the role of remote and surface phonon scattering on inter-band tunneling properties near material interfaces, and can it be tuned using heterostructure superlattice constructs in III-V material systems? Will non-equilibrium carrier distributions induced by inter-band electron tunneling result in more or less severe dissipative bottlenecks? Our research seeks to optimize both n-channel and p-channel tunnel transistor performance within the framework of a compatible device architecture so that ultra-low power complementary digital electronics can be realized with record energy-delay metric over traditional CMOS. This research is funded by the NRI (Nanoelectronics Research Initiative) and SRC under the MIND research center