Ferroelectric Hafnia for Advanced Memory: Physics, Materials, and Device Design

Jun
25

Ferroelectric Hafnia for Advanced Memory: Physics, Materials, and Device Design

Duk-Hyun Choe, Samsung Advanced Institute of Technology (SAIT)

11:00 a.m., June 25, 2026   |   119 DeBartolo Hall

The discovery of ferroelectricity in a simple binary oxide, Hf02, has sparked a resurgence of interest in ferroelectric (FE) devices. Unlike traditional ferroelectrics, Hf02-based materials are highly scalable and compatible with industrial CMOS processes. These features make them promising candidates for advanced memory and logic applications. At the same time, their ferroelectric behavior remains unconventional in several respects, and the underlying physics is still not fully understood.

Duk-Hyun Choe

Duk-Hyun Choe,
Samsung Advanced Institute of Technology (SAIT)

In this talk, I will present our theoretical and experimental approaches to harnessing FE hafnia for practical device applications. Beginning with fundamentals, I will revisit the modern theory of polarization to clarify the multivalued nature of polarization in FE HfO2. I will then introduce an atomistic picture of ultrafast switching enabled by the unique structural topology of Hf02. Turning to devices, I will highlight our recent and ongoing experimental efforts on negative-capacitance FETs, FE capacitors, and FeFETs. Finally, I will discuss how oxide-semiconductor channels can reshape the FE transistor design space, enabling co-optimized device architectures and gate stacks for both 1T DRAM and ferroelectric NAND as energy-efficient, scalable memory technologies.

Duk-Hyun Choe is a principal researcher at the Samsung Advanced Institute of Technology (SAIT), where he has served as project manager of the ferroelectric device project since 2024. He is currently a visiting scientist at MIT on an industrial sabbatical. His research focuses on the physics of ferroelectric hafnia and its implementation in ferroelectric capacitors and ferroelectric field-effect transistors for semiconductor applications. He is broadly interested in translating emerging physical phenomena into scalable device technologies and exploring new architectures that bridge logic and memory. He has received multiple honors within Samsung, including the Grand Award (2021) and Gold Award (2023) at the Samsung Best Paper Awards, as well as the Samsung DS Patent Award (2021, 2025) and Samsung DS Paper Award (2024). He earned his B.S. and Ph.D. degrees in physics from the Korea Advanced Institute of Science and Technology (KAIST) in 2009 and 2015, respectively.