Two of the most popular technologies being actively adopted by the semiconductor industry for 3D heterogeneous integration are micro-bumping and hybrid bonding. In this talk, we quantify and compare the power, performance, and area (PPA) of 3D ICs built with these two bonding technologies. Our studies are based on commercial quality GDS layouts and sign-off PPA analysis of commercial processor architectures designed with commercial process development kits (PDK). We analyze the impact of 3D interconnects enabled by micro-bumps and hybrid bond pads at various pitches on full-chip critical path delay, memory latency, and power consumption. In addition, we investigate the power delivery and thermal issues in these bonding technologies and develop solutions to mitigate the associated reliability issues. We also describe the commercial-quality RTL-to-GDS tools developed to enable these studies.
Prof. Sung Kyu Lim received Ph.D. degree from UCLA in 2000. He joined the School of Electrical and Computer Engineering at the Georgia Institute of Technology in 2001, where he is currently a professor. His research focus is on the architecture, circuit design, and electronic design automation for 3D ICs. He has published more than 400 papers on 3D ICs.