Stacked CMOS (or CFET) is a crucial option for continuing scaling in the semiconductor industry. This talk discusses the scaling benefits of stacked CMOS, process features that enable stacking transistors, and interconnects that enable cell-level connections. The first demonstration of a monolithic gate-all-around, scaled (60nm) gate pitch CFET inverter is shared. CFET device depopulation is also demonstrated as a potential feature for implementing more complex circuits. Stacked CMOS is shared as an example of how continued scaling relies on innovation in both devices and interconnects and is guided by a combination of process and design considerations.
Jami Wiedemer, Ph.D.
Memory Circuit Technology Group
Jami Wiedemer received a B.S. degree in electrical engineering from the University of Notre Dame in 2000 and her master’s and doctoral degrees in electrical engineering from Cornell University in 2004 and 2005, respectively.
In 2005, she joined Intel Corporation, Hillsboro, OR as a device engineer in Logic Technology Development, where she worked on 45nm, 22nm, and 14nm technology nodes. In 2015, she moved to the Memory Circuit Technology group, working on SRAM for 10nm and 22FFL technologies. As of 2021, she is a research engineer in Technology Research. Her current research interests include CMOS scaling, test structure design, and variation reduction.